1. Field of the Invention
The present invention relates generally to the multilayer printed wiring boards and more specifically relates to multilayer build-up substrates that include at least one light weight constraining core that is part of the electrical circuit of the printed wiring board.
2. Description of the Related Prior Art
Semiconductor device fabrication typically involves the creation of a semiconductor die using chemical processes followed by the packaging of the die. Mounting the die in the packaging includes connecting the die pad pins to the pins on the packaging. In many applications, the interconnection between the die pad pins and the pins on the packaging is achieved by directly mounting the semiconductor die to a printed wiring board (PWB) substrate. The semiconductor die and the substrate are then encapsulated within packaging and the substrate provides the connections between the die pad pins and the packaging pins.
Various direct mounting techniques are known including flip-chip mounting (FC), direct chip attach (DCA), direct die attach (DDA), and flip chip on board (FCOB). These techniques usually involve the fixing of a semiconductor die to a build-up PWB substrate. Build-up PWB substrates typically include a central constraining layer or “core” to which comparatively thin dielectric layers are attached. The thin dielectric layers include fine circuit features and narrow diameter plated vias. A core can be constructed using a glass fiber based dielectric material possessing physical characteristics similar to those of glass fiber based dielectric materials used in the construction of the type of PWB on which an integrated circuit (i.e., a packaged semiconductor device) would be surface mounted. To distinguish between PWBs on which ICs are mounted and PWB substrates, the former are referred to as conventional PWBs. The thin dielectric layers in build-up PWB substrates are constructed from a class of materials that are typically not used in the construction of conventional PWBs. Specialized processing techniques are used to bond the core and the thin dielectric layers and to form the fine circuit traces and narrow diameter plated vias.
A problem that can be encountered when using direct die mount with a PWB substrate is that thermal cycling can cause the device to fail. A significant co-efficient of thermal expansion (CTE) difference often exists between a semiconductor die material and the PWB substrate and, consequently, thermal cycling can break connections between the die and the PWB substrate. Semiconductor die materials typically have CTEs of between 2.5 ppm/° C. to 4.0 ppm/° C. A substrate including a fiberglass epoxy based constraining layer typically has a CTE of 14 ppm/° C. to 20 ppm/° C. parallel to the surface plane. The CTE mismatch between the semiconductor die and substrate material can stress connection points between the semiconductor die and the PWB substrate during thermal cycling. The stresses placed upon the connection points can be related to the distance between a connection point and a neutral point (DNP). A neutral point is a location that experiences zero displacement during thermal cycling. The larger the semiconductor, the greater the maximum DNP. Therefore, increasing semiconductor die size can cause increased stress on connection points between the semiconductor die and the substrate and ultimately reduce electrical connection reliability.
An adhesive underfill can be used to offset or reduce some of the induced stresses caused by CTE mismatch between a semiconductor die and a PWB substrate. However, when a larger semiconductor chip is mounted on a substrate, the stress reduction by underfill can be insufficient to ensure reliable contacts between the die pins and the PWB substrate.
In many applications build-up PWB substrates that include cores, which reduce the CTE of the PWB substrate, are used to construct ICs. U.S. Pat. No. 6,711,812 to Lu et al. and U.S. Patent Publication 2004/0163248 to Lu et al. describe the use of a thick copper core in a PWB substrate, which reduces the CTE of the PWB substrate. Other metal alloys that are used to reduce the CTE of PWB substrates include nickel-Iron alloys, copper-Invar-Copper (CIC), and Copper-Molybdenum-Copper (CMC). Using metals in the construction of a PWB substrate core has a tendency to increase the weight of the PWB substrate compared to the use of a fiberglass based core material. In addition, thick metal core layers are very difficult to process.
U.S. Pat. No. 6,869,665 to Tani et al., U.S. Pat. No. 7,002,080 Tani et al., and Japanese Patent publication 60-140898 to Tani et al. (the Tani. et al. references) disclose PWB substrates formed with micro-wiring structure, which are manufactured using a build-up method on a core constructed using a resin composite enclosing several pieces of carbon fiber cloth. The Tani et al. references also disclose that plated through holes extending through the core are electrically isolated from the carbon fiber cloth by cylindrical insulating resin portions formed on the wall surfaces of the through holes.
Use of a PWB substrate including a core constructed using a carbon fiber material in a manner similar to that disclosed in the Tani et al. references can provide a PWB substrate with a lower CTE than an equivalent PWB substrate with a core constructed using a glass fiber based material and, which is significantly lighter than an equivalent PWB substrate with a core constructed using a metal or metal alloy material. A potential exists, however, for PWB substrates with cores constructed using carbon fiber materials in the manner outlined in the Tani et al. references to fail when there is a high density of plated through holes extending through the core. Creating the cylindrical insulating resin portions described in the Tani et al. references involves removal of an amount of carbon fiber material from the core. As the density of through holes extending through the core increases, the amount of carbon fiber material removed also increases. Beyond a certain point, the amount of material removed can compromise the physical properties of the core.
The disclosure of U.S. Pat. No. 6,869,665 to Tani et al., U.S. Pat. No. 7,002,080 Tani et al., Japanese Patent publication 60-140898 to Tani et al., and U.S. Pat. No. 6,711,812 to Lu et al. and U.S. Patent Publication 2004/0163248 to Lu et al. is incorporated herein by reference in its entirety.